Pi 4 SoC

How is are Pis arranged internally, and how do they differ from a desktop PC?

The Pi 3 and Pi 4 are heavily optimised for being low power and low cost. The chip which includes the CPU is referred to as a SoC, "System on a Chip," as it includes many components which would traditionally be found as discrete components elsewhere on the motherboard. The Pi 5 is more conventional, in that it moves much `low' speed I/O to a separate I/O chip. The following diagrams of the SoCs are only an approximation to the truth, but show some of the key points.

Pi 5 SoC (BCM2712)

Pi 5 SoC

Pi 4 SoC (BCM2711)

Pi 4 SoC

Pi 3 SoC (BCM2710/2837)

Pi 3 SoC

The dotted line encloses everything on the SoC.

Main clock speeds

Pi 3Pi 3+Pi 4Pi 400Pi 5

One important issue for performance is barely mentioned above: the bus running between the L2 cache controller and main memory, a bus which also connects to the GPU, SDIO port, and, depending on model, much else besides. This bus is 128 bits wide, and runs at the core frequency. Thus the the Pi 4's memory can be described as running at `an effective 2000MT/s'. The memory might be able to make 32 bit transfers at 3200MT/s to the memory controller, but the path out of the controller is 128 bits at 500MT/s, so equivalent to 2000MT/s at 32 bits. The Pi 5 runs this bus at 910MT/s, equivalent to 3640MT/s at 32 bits, and still not quite as fast as its DDR4 RAM.

The Pi 4 marked a significant change from earlier Pis. The first three generations of Pi used very similar SoCs, the BCM2835 to BCM2837, with changes to clock speed and CPU being the biggest differences between them. The Pi 4 makes several other changes, in that the GPU moves from the VideoCore IV of earlier models to the VideoCore VI, the memory interface moves from DDR2/900 of the Pi 3B (DDR2/1000 in the Pi 3B+) to DDR4/3200, and the ethernet interface moves onto the SoC rather than sitting on an external USB2 bus. Also there is now a (single) PCIe link, which is used for an external USB3 controller. Earlier Pis supported USB2 only, with a single USB2 link from the SoC being shared by a USB hub and the ethernet controller.

So the Pi 4 represents a large change in the bandwidth available between the SoC and the outside world. Memory bandwidth increased by a factor of three, ethernet bandwidth by a factor of two, SD card bandwidth by a factor of two (due to a later version of the SDIO interface), USB by almost a factor of ten.

The Pi 5 represents another major redesign, with the `low' speed I/O moved to a separate chip, along with significant improvements to the CPU core, now an A76, caches, GPU, now a VideoCore VII, and faster memory too.

A generic PC

If one were to compare this to a contemporary desktop PC, then even the Pi 5 looks low on I/O capabilities. A standard PC or laptop memory bus is 128 bits wide, not 32, so even though it might still be DDR4/3200, it can supply almost 60GB/s rather than about 16GB/s. (The number after the / gives the number of millions of transfers a second the memory bus can make. However, for the Pi each transfer is four bytes, and for the average PC it is 16 bytes.) Similarly a standard SATA3 disk interface is rated at 600MB/s, far faster than the Pi 5's 100MB/s SD card interface.

Desktop block diagram

N.B. Some interfaces, such as the camera and audio interfaces, are not shown. Most of the above information is sourced from web searches, and may be a fairly weak approximation to the truth. My apologies to any Broadcom or Pi engineers who are in tears by this point. If you wish to send in corrections, please do!